1. Field of the Invention
The present invention relates generally to an interconnection layer on a semiconductor substrate, and more particularly to structure for reducing parasitic capacitance of an interconnection layer on a semiconductor substrate and a method for manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a diagram showing a plane layout of a memory portion of a dynamic MOSRAM (metal oxide semiconductor random access memory) with folded bit line structure.
In FIG. 1, the random access memory comprises active regions 14 for storing and transferring information charges, bit lines 11 each comprising a first aluminum interconnection layer electrically connected to the active regions 14 through contacts 7, cell plates 12 each serving as one electrode of a memory cell capacitor in which information charges are stored, and word lines 13 for controlling read/write operation of the information charges stored in the memory cell. A field oxide film is formed between the adjacent active regions, so that the adjacent active regions are electrically isolated from each other. More specifically, field oxide films are formed around the active regions 14. The cell plates 12 are formed outside regions enclosed by dash and dot lines, i.e., over the field oxide films. MOS transistors each having each of the word lines 13 serving as a gate electrode are formed in regions in which the cell plates 12 are not formed, so that the regions serve as transfer gates at the time of reading/writing signal charges. In the folded bit line structure as shown in FIG. 1, memory cells are connected to a single word line 13 every other bit line 11. More specifically, two bit lines constitute a bit line pair.
Description is now made on information reading operation by way of example.
When a single word line is selected, information stored in a memory cell connected to the word line 13 is read out to a bit line 11. In the conventional folded bit line structure, the potential difference between a bit line connected to the selected memory cell and a bit line referred to as complementary bit line hereinafter) connected to a non-selected memory cell, of a bit line pair is detected so that information is read out. More specifically, a reference potential appears on the complementary bit line and a potential corresponding to the information stored in the memory cell appears on the selected bit line. The difference between the potential on the bit line and the reference potential on the complementary bit line is increased so that information is read out. In general, when information is read out, an input signal is applied to a particular word line 13 as described above so that a transistor is operated, and charges stored in a memory cell are read out to a bit line 11 through a contact 7 and detected as the amount of change in potential, that is, an output signal in a sense amplifier (not shown) connected to the bit line 11. The effect of the input signal (generated by the transistor) on the output signal depending on the interconnection length of the bit line 11 from the contact 7 to the sense amplifier can not be neglected in an element which requires high-speed operation.
FIG. 2 is a diagram showing the relation associated with delay between the input signal and the output signal.
In FIG. 2, when the input signal is converted from a low level V.sub.L to a high level V.sub.H, the corresponding output signal is converted from the low level V.sub.L to the high level V.sub.H. As shown in FIG. 2, the output signal is not immediately converted from the low level V.sub.L to the high level V.sub.H but it is gradually converted from the low level V.sub.L to the high level V.sub.H after a lapse of a particular time period "t". More specifically, the input signal appears as an output signal delayed by the time period "t". Since the time delay "t" is proportional to a time constant (R.times.C=resistance.times.capacitance) of the bit line 11, the time constant must be decreased to increase the speed of an element. However, as the element is made finer and finer, an interconnection is made thinner and thinner or drawn about, so that the interconnection length tends to increase. As a result, the resistance R tends to rather increase.
On the other hand, the presence or absence of the output signal is detected as the amount of change in potential in the sense amplifier, as described above. Assuming that capacitance of a bit line is represented by C.sub.B and capacitance of a memory cell is represented by C.sub.S, the amount of change in potential which appears on the bit line 11 is a very small value obtained by C.sub.S /C.sub.B. The capacitance C.sub.B of a bit line comprises capacitance of an interconnection of the bit line itself and stray capacitance which parasitizes the capacitance of an interconnection. If the stray capacitance is increased, that is, the capacitance C.sub.B of a bit line is increased, the amount of change in potential which appears on the bit line 11 is substantially decreased, so that it becomes difficult to correctly read out information.
As described in the foregoing, the decrease of the stray capacitance in interconnection structure is very important generally in terms of operating characteristics and for the purpose of correctly reading out the information in a random access memory or the like.
FIG. 3 is a schematic cross sectional view of interconnection structure for explaining stray capacitance of an interconnection.
In FIG. 3, a field oxide film 15 having a thickness "d" is formed on a silicon substrate 1, and an interconnection 5 having a width "W" is formed thereon.
Assuming that a dielectric constant of the oxide film 15 is represented by .epsilon.and the area of contact of the interconnection 5 with the oxide film 15 is represented by S, capacitance C produced by the interconnection 5 and the silicon substrate 1 is as follows: EQU C=.epsilon..times.S/d.
Since the dielectric constant is a constant value determined by the oxide film 15, the area S must be decreased or the thickness d must be increased to decrease the capacitance C. Assuming that the interconnection length is represented by L, the relation is represented by the following equation; EQU S=L.times.W
where L depends on the layout of elements. In order to decrease the area S, it is necessary to decrease the width W of the interconnection 5 so that the interconnection 5 has a rectangular cross sectional shape in FIG. 3. However, if the width W of the interconnection 5 is decreased with the area being held constant, the thickness of the interconnection layer to be processed becomes larger in patterning the interconnection 5, so that the processability is decreased. In addition, even if the interconnection 5 is made longer in a longitudinal direction so that capacitance between the interconnection 5 and the silicon substrate 1 can be decreased, another stray capacitance of an interconnection is produced between adjacent interconnections, so that it is not advisable to form the interconnection 5 in the above mentioned rectangular shape.
Thus, assuming that the interconnection length and the cross sectional shape of the interconnection 5 are not changed, the thickness of the oxide film 15 must be increased to decrease the capacitance C. However, the following problems occur to increase the thickness of the oxide film 15;
(1) A very long oxidizing time period is required to form a thick oxide film on the entire major surface of a semiconductor substrate.
(2) Since processing for oxidation at a high temperature is continued for a long time, characteristics of the semiconductor substrate change.
(3) When impurities are ion-implanted into the semiconductor substrate by fine structure processing of the thick oxide film in the subsequent processes, a mask or the like must be patterned on a substantial stepped portion because the oxide film is thick, so that it is difficult to form a pattern with high accuracy.